The present invention relates to electronic circuits, and more particularly, to techniques for phase shifting periodic signals.
A digital periodic clock signal is often used to sample a data signal that is transmitted to an integrated circuit from an external source. Different techniques can be used to align the rising and falling edges of the clock signal with respect to a sampling window of the data signal so that the data signal can be sampled accurately. As the clock signal frequency and the data rate increases, the sampling window decreases, and the sampling timing is more constrained. A phase interpolator circuit is an example of a circuit that can be used to generate a desired phase shift in a high frequency sampling clock signal.
FIG. 1A illustrates a prior art phase shifting system. The system of FIG. 1A includes a control circuit 10, a multiplexer block 15, slew rate circuits 21-24, and analog phase interpolator 30. FIG. 1B illustrates details of analog phase interpolator (API) 30. Phase interpolator 30 includes two differential pairs formed by n-channel metal oxide semiconductor field-effect transistors (MOSFETs) 41-44, variable current sources 51-52, resistors 61-62, and voltage comparator 71.
A phase interpolator circuit can generate any one of a number of different phases in a periodic output signal relative to the phases of periodic input signals. A phase interpolator circuit can generate a sinusoidal output voltage signal VOUT that is a weighted sum of two sinusoidal voltage input signals, as shown in equations (1)-(3).VOUT=R×[(α×sin(ωt))+(β×cos(ωt))]=C×sin(ωt+θ)  (1)
                    C        =                  R          ×                                                    α                2                            +                              β                2                                                                        (        2        )            θ=Arctan(β/α)  (3)
In equations (1) and (2), R is the resistance of resistor 61, R is also the resistance of resistor 62, α and β are the currents through current sources 51-52, respectively, and w is the angular frequency of the periodic input signals of the phase interpolator. The phase interpolator can generate a phase shift θ in VOUT between 0° and 360° relative to the periodic input signals. A desired phase shift in VOUT can be generated by setting the values of α and β as a weighted summation of two variable current sources 51-52.
In the system of FIG. 1A, multiplexers in multiplexer block 15 select four of the clock signals C0, C45, C90, C135, C180, C225, C270, and C315 as output clock signals CLKA, CLKB, CLKC, and CLKD based on control signals CS1 from control circuit 10. The four selected clock signals CLKA, CLKB, CLKC, and CLKD are transmitted to slew rate circuits 21-24. Slew rate circuits 21-24 convert clock signals CLKA, CLKB, CLKC, and CLKD into four signals A, B, C, and D that are more sinusoidal in shape. The four sinusoidal signals A-D are transmitted to the gate terminals of transistors 41-44 in phase interpolator 30, respectively. Voltage comparator 71 generates periodic output signals OUT and OUTB at its differential outputs based on the voltage drops generated across resistors 61-62.
The four selected clock signals CLKA, CLKB, CLKC, and CLKD determine which of 8 different 45° wide regions RG0-RG7 between 0° and 360° the phase shifts in OUT and OUTB occur in. FIG. 1C illustrates the 8 regions RG0-RG7 between 0° and 360°. Clock signals C0, C45, C90, C135, C180, C225, C270, and C315 have relative phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Multiplexer circuits 101-112 in multiplexer block 15 select the 4 clock signals shown in one of columns 2-9 of Table 1 below as clock signals CLKA, CLKB, CLKC, and CLKD based on control signals CS1 to generate a phase shift in output signal OUT that is within the region RG0-RG7 indicated in the top row of that column. Output signal OUTB is the inverse of output signal OUT.
TABLE 1Input SignalRG0RG1RG2RG3RG4RG5RG6RG7AC0C45C90C135C180C225 C270C315BC180 C225C270C315C0C45C90C135CC45C90C135C180C225C270C315 C0DC225 C270C315C0C45C90C135C180
Control circuit 10 generates control signals CS2 and CS3 for controlling the weight current ratios of current sources 51-52, respectively. Control circuit 10 generates control signals CS1 for selecting the regions RG0-RG7 that the phases of OUT and OUTB are generated in. The currents through current sources 51-52 are varied to change the phase shift of OUT and OUTB within the selected regions RG0-RG7.